1. Field of the Invention
The present invention relates to a control signal generator, a latch circuit, a flip-flop including the latch circuit and the control signal generator and a method for controlling operations in the flip-flop.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional pulse-based flip-flop 100. In general, the conventional pulse-based flip-flop 100 is designed to operate at substantially fast speeds. The pulse-based flip-flop 100 typically includes a pulse generator 110 for generating complementary pulses C and CB (the pulses C and CB are complements of each other and may also be referred to as the normal and complement outputs of flip-flop 100, respectively) and a latch 130 latching an input signal (or data DIN) based on the complementary pulses to generate an output or result of the latching operation (DOUT).
FIG. 2 is a circuit diagram of the pulse generator 110. The pulse generator 110 typically includes a plurality of inverters 111, 113, 115, and 119 and a NAND gate 117. The NAND gate 117 receives a clock signal CLK and a delayed clock signal (delayed by the inverter chain 111, 113, and 115), combines the two clock signals in a NAND operation, and outputs a result of the NAND operation as a pulse CB. The inverter 119 inverts the pulse CB output by the NAND gate 117 and outputs a pulse C, as shown in FIG. 2.
FIG. 3 is a circuit diagram of the latch 130. Referring to FIG. 3, the latch 130 of the conventional flip-flop 100 typically includes two tri-state buffers 131 and 137 and two inverters 133 and 135. The latch 130 generally receives the input signal DIN through an input port (at tri-state buffer 131) based on logic states of the complementary pulses C and CB, latches the input signal DIN, and outputs a result of the latching as an output signal DOUT.
A semiconductor chip typically may include a plurality of flip-flops that are packaged together. Since these flip-flops are packaged, the logics (e.g., logic circuits associated with flip-flops) existing in the chip may not be able to be properly tested. This is because accurate detection of whether each of the flip-flops in the chip are properly operating has proven to be substantially difficult.
Accordingly, each of the conventional flip-flops in the chip typically include a dedicated circuit to test whether the flip-flop operates properly, in addition to a latch circuit for latching a signal (or data). This dedicated circuit is referred to as a scan circuit. A flip-flop including a scan circuit may be commonly referred to as a flip-flop with scanning function.
However, the inclusion of a scan circuit in a flip-flop may increase power consumption of the flip-flop. Additionally, setup time for the flip-flop may increase, which may contribute to a greater input-to-output delay through the flip-flop. Consequently, this may lead to a reduction in operating speed of a semiconductor chip that includes a flip-flop with scanning function.